Trench capacitors and memory cells using trench capacitors and method of fabricating same

ABSTRACT

A trench structure, a method of forming the trench structure, a memory cell using the trench structure and a method of forming a memory cell using the trench structure. The trench structure includes: a substrate; a trench having contiguous upper, middle and lower regions, the trench extending from a top surface of said substrate into said substrate; the upper region of the trench having a vertical sidewall profile; and the middle region of the trench having a tapered sidewall profile.

FIELD OF THE INVENTION

The present invention relates to the field of semiconductor devices;more specifically, it relates to semiconductor trench capacitors andmemory cells using the trench capacitors and method of fabricating thesemiconductor trench capacitors and memory cells using the trenchcapacitors.

BACKGROUND OF THE INVENTION

A predominate use of trench capacitors is as the storage nodes ofdynamic random access memory (DRAM) cells, though there are many otheruses. As the density of DRAM increases and the photolithographicgroundrules and resultant physical dimensions of the trench capacitorsdecrease, it has become increasingly difficult to fabricate theresultant narrow trenches. Additionally, narrow trenches have lowercapacitance and higher resistance than wide trenches leading to lowerreliability. Therefore, there is a need for trench capacitor structuresand a method of fabricating trench capacitors that is scalable to everdecreasing trench widths and that overcomes fabrication limits andcapacitance and resistance problems of current trench capacitor designs.

SUMMARY OF THE INVENTION

A first aspect of the present invention is a structure, comprising: asubstrate having a top surface defining a horizontal direction; a trenchhaving contiguous upper, middle and lower regions, the middle regionbetween the upper and lower regions, the trench extending from the topsurface of the substrate into the substrate along an axis perpendicularto the top surface of the substrate, the axis defining a verticaldirection; the upper region of the trench adjacent to the top surface ofthe substrate having a vertical sidewall profile and a first width inthe horizontal direction; and the middle region of the trench having atapered sidewall profile, a width in the horizontal direction of themiddle region at a juncture of the upper region and the middle regionbeing the first width and being greater than a second width in thehorizontal direction of the middle region at a juncture of the middleregion and the lower region.

A second aspect of the present invention is a method forming a trench ina substrate having a top surface defining a horizontal direction,comprising: forming a masking layer on the top surface of the substrate;forming an opening in the masking layer to define a perimeter of atrench; and forming the trench in the substrate through the opening, thetrench having contiguous upper, middle and lower regions, the middleregion between the upper and lower regions, the trench extending fromthe top surface of the substrate into the substrate along an axisperpendicular to the top surface of the substrate, the axis defining avertical direction, the upper region of the trench adjacent to the topsurface of the substrate having a vertical sidewall profile and a firstwidth in the horizontal direction, the middle region of the trenchhaving a tapered sidewall profile, a width in the horizontal directionof the middle region at a juncture of the upper region and the middleregion being the first width and being greater than a second width inthe horizontal direction of the middle region at a juncture of themiddle region and the lower region.

A third aspect of the present invention is a memory cell, comprising: atrench capacitor in a substrate, the trench capacitor having contiguousupper, middle and lower regions, the middle region between the upper andlower regions, the trench extending from a top surface of the substrateinto the substrate along an axis perpendicular to the top surface of thesubstrate, the axis defining a vertical direction; the upper region ofthe trench adjacent to the top surface of the substrate having avertical sidewall profile; the middle region of the trench having atapered sidewall profile, a width in the horizontal direction of themiddle region at a juncture of the upper region and the middle regionbeing greater than a width in the horizontal direction of the middleregion at a juncture of the middle region and the lower region; and afield effect transistor comprising a gate electrode separated from achannel region in the substrate by a gate dielectric layer on the topsurface of the substrate and first and second source/drains formed inthe substrate on opposite side of the channel region, the secondsource/drain electrically connected to an electrode formed in thetrench.

A fourth aspect of the present invention is a method of fabricating amemory cell, comprising: forming a trench capacitor in a substrate, thetrench capacitor having contiguous upper, middle and lower regions, themiddle region between the upper and lower regions, the trench extendingfrom a top surface of the substrate into the substrate along an axisperpendicular to the top surface of the substrate, the axis defining avertical direction; the upper region of the trench adjacent to the topsurface of the substrate having a vertical sidewall profile; the middleregion of the trench having a tapered sidewall profile, a width in thehorizontal direction of the middle region at a juncture of the upperregion and the middle region being greater than a width in thehorizontal direction of the middle region at a juncture of the middleregion and the lower region; and forming a field effect transistorcomprising a gate electrode separated from a channel region in thesubstrate by a gate dielectric layer on the top surface of the substrateand first and second source/drains formed in the substrate on oppositeside of the channel region, the second source/drain electricallyconnected to an electrode formed in the trench.

BRIEF DESCRIPTION OF DRAWINGS

The features of the invention are set forth in the appended claims. Theinvention itself, however, will be best understood by reference to thefollowing detailed description of an illustrative embodiment when readin conjunction with the accompanying drawings, wherein:

FIGS. 1A through 1H are cross-sectional drawings illustratingfabrication of trench capacitors according to the embodiments of thepresent invention;

FIG. 2 is a cross-sectional view of a memory cell using trenchcapacitors according to the embodiments of the present invention; and

FIGS. 3A, 3B and 3C are cross-sectional views illustrating alternativelower region trench geometries of trench capacitors according to theembodiments of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

FIGS. 1A through 1H are cross-sectional drawings illustratingfabrication of trench capacitors according to the embodiments of thepresent invention. In FIG. 1A, on a top surface 100 of a siliconsubstrate 105 a pad layer 115 is formed and a trench 120 is etched inthe substrate through an opening formed in the pad layer. Pad layer 115,serves, among other uses, as a hardmask layer. Trench 120 has threedistinct regions, an upper region 125 adjacent to top surface 100 ofsubstrate 105, a middle region 130 and a lower region 135. In oneexample, pad layer 115 comprises a layer of silicon dioxide betweenabout 2 nm and about 10 nm in thickness in contact with top surface 100and a silicon nitride layer between about 100 nm and 2000 nm on thesilicon dioxide layer. Additional one or more hardmask layers (notshown) can be formed on the pad layer 115 before the deep trench isetched. For example, a layer (not shown) comprising borosilicate glass(BSG) can be deposited on the pad layer 115 by chemical vapor deposition(CVD) and patterned along with the underlying pad layer 115. Theadditional hardmask layers facilitate the deep trench formation and canbe removed after the deep trench 120 is etched.

Upper region 125 of trench 120 has a substantially uniform width W1along an axis 136 perpendicular to top surface 100. Upper region 125 oftrench 120 extends a distance D1 into substrate 105. Sidewall region 137of upper region 125 of trench 120 is at an angle a1 relative to topsurface 100 of substrate 105. Sidewall region 137 of upper region 125 oftrench 120 is substantially perpendicular to top surface 100 ofsubstrate 105. In one example, angle a1 is about 90°. In one example,angle a1 is between about 89.5° and about 90.5°. Sidewall region 137 isessentially a trench region having a vertical sidewall (relative to topsurface 100).

Middle region 130 of trench 120 has width W1 where the middle regionadjoins upper region 125 and a width W2 where it adjoins lower region135. Middle region 130 extends a distance D2 into substrate 100 belowupper region 125. W1 is greater than W2. Sidewall region 138 of middleregion 135 is at an angle a2 relative to top surface 100 of substrate105. Sidewall region 138 of middle region 130 of trench 120 tapersinward toward axis 122. In one example, angle a2 is about 1.0°. In oneexample, angle a2 is between about 3.0° and about 0.5°. In one example,the ratio (W1−W2)/W1 is less than about 0.2. In one example, W1−W2 isless than or equal to about 10 nm. In one example, W1 is equal to lessthan about 90 nm and W2 is equal to or less than about 80 nm. In oneexample, W1 is equal to less than about 65 nm and W2 is equal to or lessthan 55 nm. Sidewall region 138 is essentially a trench region having atapered sidewall (relative to top surface 100). In one example D1 isbetween about four times and about five times D2.

Lower region 135 of trench 120 has width W2 where the lower regionadjoins middle region 130 and a width W2 where it adjoins lower region135. Lower region 135 of trench 120 has a substantially uniform width W2along axis 136 and extends a distance D3 into substrate 105 below middleregion 130. Sidewall region 139 of lower region 135 of trench 120 isessentially perpendicular to top surface 100 of substrate 100 in FIG.1A. Sidewall region 139 is essentially a sidewall region having avertical sidewall (relative to top surface 100). However, othergeometries of lower region 135 are possible and are illustrated in FIGS.3A, 3B and 3C and described infra.

Trench 120 may be formed by a reactive ion etch (RIE) process using amultiple step RIE process. Upper region 125 of trench 120 may be formedby a first RIE process step, middle region 130 of the trench may beformed by a second RIE process step different from the first RIE stepprocess and lower region 135 of the trench may be formed by one or moreadditional RIE process steps. Table I illustrates exemplary first andsecond RIE process steps.

TABLE I Exemplary RIE Process Steps for a Trench with W1 less than orequal to 90 nm (300 mm Wafer, about 20% Trench Area) Trench Region UpperMiddle Lower RIE Step 1 Step 2 Step 3 Bias power (W) 1300 1500 1800Pressure (mT) 150 150 200 O₂ (sccm) 28 23 16 NF₃ (sccm) 36 36 32 HBr(sccm) 300 300 300 Profile of Region Vertical Tapered Vertical Depth ofRegion (um) 1.2 (D1) 0.3 (D2) 6.0 (D3)

A person of ordinary skill in the art, will be able to modify theconditions given in Table I to fit other trench profiles and geometrieswithout undue experimentation.

In FIG. 1B, a node dielectric layer 140 is formed on a sidewall 145(includes sidewall regions 137, 138 and 139 illustrated in FIG. 1A anddescribed supra) of trench 120, on a bottom 150 of the trench and on atop surface 155 of pad layer 1 15. In one example node dielectric isformed by low pressure chemical vapor deposition (LPCVD) of siliconnitride between about 2.5 nm and about 6.0 nm thick followed by anoptional thermal oxidation. In one example, node dielectric comprises ahigh-k (dielectric constant) material between about 0.5 nm and about 6.0nm thick formed by atomic layer deposition (ALD) or metalorganicchemical vapor deposition (MOCVD), examples of which include but are notlimited metal oxides such as Ta₂O₅, BaTiO₃, HfO₂, ZrO₂, Al₂O₃, or metalsilicates such as HfSi_(x)O_(y) or HfSi_(x)O_(y)N_(z) or combinations oflayers thereof. A high-k dielectric material has a relative permittivityabove about 10.

In FIG. 1C, trench 120 is filled with a first electrically conductivefill material 160. In one example, the first fill material 160preferably comprises N-type doped polysilicon. Alternatively, first fillmaterial 160 may comprise electrically conductive materials, includingbut not limited to, doped silicon germanium, , tungsten, titanium,cobalt, copper, aluminum, other metals, tungsten silicide, titaniumnitride, polysilicon and combinations thereof. In some cases, when firstfill material 160 is polysilicon, a void 165 may form in the polysiliconin upper region 125 of trench 120.

Because the upper part of the trench is vertical for a significantdistance before is tapers down, filling of the trench with polysiliconis more easily accomplished and any voids formed do not extend farenough into the tapered portion of the trench and can be removed ortheir disruption of fill interfaces drastically reduced duringsubsequent processing steps.

In FIG. 1D, a portion of first polysilicon 160 is removed from trench120 so that a top surface 167 of first polysilicon 160 is within middleregion 130 of trench 167. Top surface 167 is a distance D4 from the topof middle region 130. Node dielectric layer 140 is also removed from allsurfaces (particularly sidewall 145 of trench 120) no longer protectedby first polysilicon 160. In one example, first polysilicon 160 isremoved by a recess RIE process. In one example, achemical-mechanical-polish (CMP) is performed to coplanarize a topsurface of first polysilicon 160 in trench 120 with atop surface 155 ofpad layer 115 prior to a recess RIE process. In one example, nodedielectric 140 (if not removed during the recess RIE) is removed by wetetching with an etchant of hydrofluoric acid mixed with ethylene glycol.

In FIG. 1E, a dielectric collar 170 is formed on sidewall 145 wheresidewall 145 is not covered by node dielectric 140 and first polysilicon160. In one example, collar 170 is formed by CVD deposition of atetraethoxysilane (TEOS) oxide followed by an RIE process and is betweenabout 15 nm and about 50 nm thick. In one example, a thermal oxidationprocess is performed to form a silicon dioxide (not shown) on theexposed sidewall 145 and on the top surface of the polysilicon 160 priorto the TEOS deposition. In one example, an annealing process at atemperature between 800° C. to 1200° C. is performed prior to the RIEprocess. In one example, collar 170 comprises a low-k (dielectricconstant) material, examples of which include but are not limited tohydrogen silsesquioxane polymer (HSQ), methyl silsesquioxane polymer(MSQ), SiLK™ (polyphenylene oligomer) manufactured by Dow Chemical,Midland, Tex., Black Diamond™ (methyl doped silica or SiO_(x)(CH₃)_(y)or SiC_(x)O_(y)H_(y) or SiOCH) manufactured by Applied Materials, SantaClara, Calif., organosilicate glass (SiCOH), and porous SiCOH betweenabout 15 nm and about 40 nm thick. A low-k dielectric material has arelative permittivity of about 3.1 or less.

Because the upper part of the trench is vertical for a significantdistance before is tapers down, formation of collars is easilyaccomplished and the collars may be kept relatively thick with no fearof reducing the cross-sectional area of the polysilicon fill which wouldincrease the resistance of the capacitor.

In FIG. 1F, trench 120 is filled with a second electrically conductivefill material 175 and then second fill material is recessed back so atop surface 177 of second fill material 175 is within upper region 125of trench 120 in a manner similar to that described supra for recessingfirst fill material 160. In one example, second fill material 175preferably comprises N-type doped polysilicon. Alternatively, secondfill material 1750 may comprise electrically conductive materials,including but not limited to, doped silicon germanium, , tungsten,titanium, cobalt, copper, aluminum, other metals, tungsten silicide,titanium nitride, polysilicon and combinations thereof.

In FIG. 1G, collar 170 is removed from sidewall 145 where the collar isnot protected by second polysilicon 175. Dry etch processing (such asplasma etching) or wet etch processing (such as etching in hydrofluoricacid containing etchants) may be used depending on the composition ofcollar 170.

In FIG. 1H, trench 120 is filled with a third electrically conductivefill material 180 and then the third fill material recessed back so atop surface 182 of the second fill material is within upper region 125of trench 120 but below top surface 100 of substrate 105 in a mannersimilar to that described supra for recessing first fill material 160.In one example, third fill material 180 preferably comprises N-typedoped polysilicon. Alternatively, first fill material 160 may compriseelectrically conductive materials, including but not limited to, dopedsilicon germanium, , tungsten, titanium, cobalt, copper, aluminum, othermetals, tungsten silicide, titanium nitride, polysilicon andcombinations thereof.

Fabrication of a trench capacitor 185 according to the embodiments ofthe present invention is essentially complete. Additional steps,described infra, may be performed to fabricate a dynamic access memory(DRAM) cell.

FIG. 2 a cross-sectional view of a memory cell using trench capacitorsaccording to the embodiments of the present invention. In FIG. 2, atrench isolation 190 is formed in substrate 105 and partially intotrench capacitor 185. In one example, trench isolation 190 may be formedby (1) etching trenches into substrate 105 and into a portion of trenchcapacitor 185, using pad layer 115 (see FIG. 1H) as a hardmask, (2)over-filling the trench with a dielectric material, such as TEOS oxideand (3) performing a CMP down to the pad layer.

Next, pad layer 115 (see FIG. 1H) is removed and a field effecttransistor (FET) 200 is formed adjacent to and physically andelectrically connected to trench capacitor 185. Formation of FETs iswell known in the art. FET 200 includes a gate electrode 205 anddielectric spacers 210 formed over a gate dielectric 215 formed over achannel region 220 separating a first source/drain 225 from a secondsource/drain 230. A buried strap 235 (formed by out-diffusion of dopantsfrom third polysilicon 180 provides an electrical connection betweensecond source/drain 230 and third polysilicon 180. In one example. FET200 is an n-channel FET (NFET).

FIGS. 3A, 3B and 3C are cross-sectional views illustrating alternativelower region trench geometries of trench capacitors according to theembodiments of the present invention. Any of the trenches 120A, 120B or120C of respective FIGS. 3A, 3B and 3C may replace trench 120 of FIG. 1Aas the starting trench for the fabrication of a trench capacitoraccording to the embodiments of the present invention.

In FIG. 3A, upper and middle regions 125 and 130 of trench 120A are thesame as upper and middle regions 125 and 130 of trench 120 of FIG. 1A. Alower region 135A of trench 120A has an inward tapering sidewall region139A so a width W3 at the bottom of the lower region is less than thewidth W2 at the top of the lower region.

In FIG. 3B, upper and middle regions 125 and 130 of trench 120B are thesame as upper and middle regions 125 and 130 of trench 120 of FIG. 1A. Alower region 135B of trench 120B has an outward tapering sidewall region139B so a width W4 at the bottom of the lower region is greater than thewidth W2 at the top of the lower region.

In FIG. 3C, upper and middle regions 125 and 130 of trench 120C are thesame as upper and middle regions 125 and 130 of trench 120 of FIG. 1A. Alower region 135C of trench 120C includes a vertical region 240 and abulbous region 245 (the vertical region is between middle region 130 andbulbous region 245). Vertical region 240 has a width W2 and bulbousregion 245 has a maximum width W5, where W5 is greater than W2. Trenches120B and 120C are known as a “bottle” trenches and when used for atrench capacitor results in a “bottle trench capacitor.”

Thus the present invention provides trench capacitor structures and amethod of fabricating trench capacitors that is scalable to everdecreasing trench widths and that overcomes fabrication limits andcapacitance and resistance problems of current trench capacitor designs.

The description of the embodiments of the present invention is givenabove for the understanding of the present invention. It will beunderstood that the invention is not limited to the particularembodiments described herein, but is capable of various modifications,rearrangements and substitutions as will now become apparent to thoseskilled in the art without departing from the scope of the invention.Therefore, it is intended that the following claims cover all suchmodifications and changes as fall within the true spirit and scope ofthe invention.

1. A structure, comprising: a substrate having a top surface defining ahorizontal direction; a trench having contiguous upper, middle and lowerregions, said middle region between said upper and lower regions, saidtrench extending from said top surface of said substrate into saidsubstrate along an axis perpendicular to said top surface of saidsubstrate, said axis defining a vertical direction; said upper region ofsaid trench adjacent to said top surface of said substrate having avertical sidewall profile and a first width in said horizontaldirection; and said middle region of said trench having a taperedsidewall profile, a width in said horizontal direction of said middleregion at a juncture of said upper region and said middle region beingsaid first width and being greater than a second width in saidhorizontal direction of said middle region at a juncture of said middleregion and said lower region.
 2. The structure of claim 1, wherein saidupper region has a uniform width in said horizontal direction from saidtop surface of said substrate to said middle region.
 3. The structure ofclaim 1, wherein designating said first width as W1 and said secondwidth as W2, the ratio of (W1−W2)/W1 is less than or equal to 0.2. 4.The structure of claim 1, further including: said lower region of saidtrench having a vertical sidewall profile.
 5. The structure of claim 1,further including: said lower region of said trench having a taperedsidewall profile, a width in said horizontal direction of said lowerregion at a juncture of said lower region and said middle region beingsaid second width and being greater than a third width in saidhorizontal direction of said lower region at a bottom of said trench. 6.The structure of claim 1, further including: said lower region of saidtrench having a tapered sidewall profile, a width in said horizontaldirection of said lower region at a juncture of said lower region andsaid middle region being said second width and being less than a thirdwidth in said horizontal direction of said lower region at a bottom ofsaid trench
 7. The structure of claim 1, further including: said lowerregion having a vertical region abutting said middle region and abulbous bottom region abutting said vertical region, said verticalregion having vertical sidewall profile and said second width in saidhorizontal direction, said bulbous region having a maximum width in saidhorizontal direction that is greater than said second width.
 8. A methodforming a trench in a substrate having a top surface defining ahorizontal direction, comprising: forming a masking layer on said topsurface of said substrate; forming an opening in said masking layer todefine a perimeter of a trench; and forming said trench in saidsubstrate through said opening, said trench having contiguous upper,middle and lower regions, said middle region between said upper andlower regions, said trench extending from said top surface of saidsubstrate into said substrate along an axis perpendicular to said topsurface of said substrate, said axis defining a vertical direction, saidupper region of said trench adjacent to said top surface of saidsubstrate having a vertical sidewall profile and a first width in saidhorizontal direction, said middle region of said trench having a taperedsidewall profile, a width in said horizontal direction of said middleregion at a juncture of said upper region and said middle region beingsaid first width and being greater than a second width in saidhorizontal direction of said middle region at a juncture of said middleregion and said lower region.
 9. The method of claim 8, wherein formingsaid trench includes: performing a first reactive ion etch process, saidfirst reactive ion etch process defining said vertical sidewall profileof said upper region; performing a second reactive ion etch processdifferent from said first reactive ion etch process, said secondreactive ion etch process defining said tapered sidewall profile of saidmiddle region; and performing one or more additional reactive ion etchprocesses, said one or more additional reactive ion etch processesdefining a sidewall profile of said lower region.
 10. The method ofclaim 8, further including said lower region of said trench having avertical sidewall profile; or said lower region of said trench having afirst tapered sidewall profile, a width in said horizontal direction ofsaid lower region at a juncture of said lower region and said middleregion being said second width and being greater than a third width insaid horizontal direction of said lower region at a bottom of saidtrench; or said lower region of said trench having a second taperedsidewall profile, said width in said horizontal direction of said lowerregion at said juncture of said lower region and said middle regionbeing said second width and being less than said third width in saidhorizontal direction of said lower region at said bottom of said trench;or said lower region having a vertical region abutting said middleregion and a bulbous bottom region abutting said vertical region, saidvertical region having a vertical sidewall profile and said second widthin said horizontal direction, said bulbous region having a maximum widthin said horizontal direction that is greater than said second width. 11.A memory cell, comprising: a trench capacitor in a substrate, saidtrench capacitor having contiguous upper, middle and lower regions, saidmiddle region between said upper and lower regions, said trenchextending from a top surface of said substrate into said substrate alongan axis perpendicular to said top surface of said substrate, said axisdefining a vertical direction; said upper region of said trench adjacentto said top surface of said substrate having a vertical sidewallprofile; said middle region of said trench having a tapered sidewallprofile, a width in said horizontal direction of said middle region at ajuncture of said upper region and said middle region being greater thana width in said horizontal direction of said middle region at a junctureof said middle region and said lower region; and a field effecttransistor comprising a gate electrode separated from a channel regionin said substrate by a gate dielectric layer on said top surface of saidsubstrate and first and second source/drains formed in said substrate onopposite side of said channel region, said second source/drainelectrically connected to an electrode formed in said trench.
 12. Thememory cell of claim 11, further including: a node dielectric layerformed on a sidewall of said trench in said lower region and on a lowerportion of said middle region, said lower portion of said middle regioncontiguous with said lower region.
 13. The memory cell of claim 11,further including: a dielectric collar formed on a sidewall of saidtrench in a lower portion of said upper region and on an upper portionof said middle region, said lower portion of said upper regioncontiguous with said upper portion of said middle region.
 14. The memorycell of claim 13, wherein said second source/drain is electricallyconnected to said electrode by a buried strap, said buried strapextending from said electrode through a notch in said collar in saidupper region of said trench to said second source/drain.
 15. The memorycell of claim 11, further including said lower region of said trenchhaving a vertical sidewall profile; or said lower region of said trenchhaving a first tapered sidewall profile, a width in said horizontaldirection of said lower region at a juncture of said lower region andsaid middle region being greater than a width in said horizontaldirection of said lower region at a bottom of said trench; or said lowerregion of said trench having a second tapered sidewall profile, saidwidth in said horizontal direction of said lower region at said junctureof said lower region and said middle region being less than said widthin said horizontal direction of said lower region at said bottom of saidtrench; or said lower region having a vertical region having a verticalsidewall profile and abutting said middle region and a bulbous bottomregion abutting said vertical region, said bulbous region having amaximum width in said horizontal direction that is greater than a widthin said horizontal direction of said vertical region.
 16. A method offabricating a memory cell, comprising: forming a trench capacitor in asubstrate, said trench capacitor having contiguous upper, middle andlower regions, said middle region between said upper and lower regions,said trench extending from a top surface of said substrate into saidsubstrate along an axis perpendicular to said top surface of saidsubstrate, said axis defining a vertical direction; said upper region ofsaid trench adjacent to said top surface of said substrate having avertical sidewall profile; said middle region of said trench having atapered sidewall profile, a width in said horizontal direction of saidmiddle region at a juncture of said upper region and said middle regionbeing greater than a width in said horizontal direction of said middleregion at a juncture of said middle region and said lower region; andforming a field effect transistor comprising a gate electrode separatedfrom a channel region in said substrate by a gate dielectric layer onsaid top surface of said substrate and first and second source/drainsformed in said substrate on opposite side of said channel region, saidsecond source/drain electrically connected to an electrode formed insaid trench.
 17. The method of claim 16, further including: forming anode dielectric layer on a sidewall of said trench in said lower regionand on lower portion of said middle region, said lower portion of saidmiddle region contiguous with said lower region.
 18. The method of claim16, further including: forming a dielectric collar on a sidewall of saidtrench in a lower portion of said upper region and on an upper portionof said middle region, said lower portion of said upper regioncontiguous with said upper portion of said middle region.
 19. The methodof claim 18, wherein said second source/drain is electrically connectedto said polysilicon electrode by a buried strap, said buried strapextending from said electrode through a notch in said collar in saidupper region of said trench to said second source/drain.
 20. The methodof claim 16, further including said lower region of said trench having avertical sidewall profile; or said lower region of said trench having afirst tapered sidewall profile, a width in said horizontal direction ofsaid lower region at a juncture of said lower region and said middleregion being greater than a width in said horizontal direction of saidlower region at a bottom of said trench; or said lower region of saidtrench having a second tapered sidewall profile, said width in saidhorizontal direction of said lower region at said juncture of said lowerregion and said middle region being less than said width in saidhorizontal direction of said lower region at said bottom of said trench;or said lower region having a vertical region having a vertical sidewallprofile and abutting said middle region and a bulbous bottom regionabutting said vertical region, said bulbous region having a maximumwidth in said horizontal direction that is greater than a width in saidhorizontal direction of said vertical region.